Xilinx USB JTAG Programmer Guide
A Xilinx USB JTAG programmer is a small purchase that is annoying to get wrong: the protocol is standard, but the connectors, the voltage range and the protection circuitry are not. This guide covers what to check before you buy, and how to get the cable working the first time you plug it in.
The protocol is standard, so what actually differs?
JTAG is defined by IEEE 1149.1 and uses four signals — TCK, TDI, TDO and TMS. Any compliant cable can talk to any compliant device. That means the differences between cables are all in the practical details:
- Target voltage range. The single most common reason a cable “does not work” is a JTAG bank running at a voltage the cable does not support.
- Connectors. Boards use 14-pin 2 mm, 10-pin 2 mm and 10-pin 2.54 mm headers, and they are physically incompatible.
- Protection. A live bench means ESD and accidental shorts. Overcurrent and ESD protection is the difference between a failed download and a dead target board.
- Toolchain support. Confirm the vendor toolchain you actually use is supported by name.
Check the voltage range against your board
Xilinx FPGAs and CPLDs commonly run their JTAG I/O between 1.5 V and 3.3 V, but boards vary with how the banks are supplied. A cable that covers 1.5 V to 5.0 V DC removes the question entirely: it will work with the low-voltage banks and with older 5 V-tolerant designs.
If you only ever work on one board family, a narrower cable is fine. If you work on other people’s boards, buy the wider range.
Get the connector right — or carry an adapter
| Header | Where you meet it |
|---|---|
| 14-pin 2 mm | Xilinx development boards and many production boards |
| 10-pin 2 mm | Compacter designs, some third-party boards |
| 10-pin 2.54 mm | Older and hobbyist boards |
Rather than buying three cables, look for one that ships with an adapter board covering all three. Check the pitch as well as the pin count — 2 mm and 2.54 mm headers are visually similar and mechanically incompatible.
Confirm toolchain support explicitly
“Xilinx compatible” is not specific enough. The two toolchains that matter are:
- Vivado — the current toolchain, including the Hardware Manager and the debug cores.
- ISE 13/14 — still in use for older device families that Vivado does not support.
If you maintain legacy designs, check that ISE is supported as well — the driver stacks are different, and a cable that works in Vivado is not automatically installed for ISE.
First use: a five-minute checklist
- Fit the right adapter for the header pitch.
- Power the target board. JTAG does not supply the target.
- Plug the cable directly into a USB port, not an unpowered hub.
- Open Vivado → Hardware Manager → Open Target → Auto Connect. On Linux, install the cable drivers first.
- Confirm the device Vivado reports is the device on your board, then program.
One cable that covers the usual cases
Our Xilinx USB JTAG programmer is built for exactly this: USB 2.0 High Speed, a 1.5 V to 5.0 V DC target range, overcurrent protection, ESD protection on the I/O, and a multi-connector adapter board covering 14-pin 2 mm, 10-pin 2 mm and 10-pin 2.54 mm headers. It is an independent, Xilinx-compatible programmer, not affiliated with or endorsed by Xilinx.
Related
- Step-by-step programming guide — from wiring to bitstream download.
- JTAG programmer for Vivado — cable drivers and the errors they cause.