Xilinx JTAG Compatibility: Target Voltages and Connectors

A JTAG programmer does not set the signal voltage — the target board does. The cable reads the board’s reference voltage on the VREF pin and drives TCK, TMS and TDI at that same level. So the question “will this programmer work with my board?” is really the question “what voltage does my board’s JTAG rail run at?”

This page lists the JTAG supply rail and the supported voltage for each Xilinx device family we could verify against AMD documentation, together with the connector pinout and the VREF conditions that apply.

Short answer: the BJ-JTAG-1 accepts a target I/O voltage of 1.5 V to 5.0 V DC.

How the JTAG voltage is set

• The JTAG pins are powered by a rail on the target board. Which rail depends on the family: VCCO_0 (also called VCC_CONFIG), VCCAUX, or VCCIO.
• The programmer reads that rail through VREF and drives its outputs at the same level. TDO is driven by the target.
• The cable therefore follows the board. A board running at 1.8 V is programmed at 1.8 V.

This is why a programmer is specified by a VREF input range, not by a single voltage.

Two different kinds of number

It is worth separating two things that are easy to conflate:

• What the programmer accepts. The BJ-JTAG-1 accepts a continuously variable target voltage, 1.5 V to 5.0 V DC. It has no discrete steps — it follows the board’s VREF, so any level in that span works.
• What the device supports. A Xilinx device runs its configuration/JTAG interface at specific levels given in its own data sheet, determined by the device specification and the board design.

The table below describes the device side. The last-but-one column is the only place where the two meet.

Compatibility table

† Virtex-4, Virtex-5 and Virtex-6 take the JTAG level from VCCO_0 (VCC_CONFIG). The level is a board design decision, not something a cable sets — check the data sheet for your family (DS302, DS202, DS152 respectively) for the levels your design supports. For Virtex-6, note that VCCO is specified to a maximum of 2.625 V, so 3.3 V I/O is not available.

‡ UltraScale uses a configuration bank whose numbering differs from 7 series. Per UG570, configuration interfaces can be powered at 1.5 V, 1.8 V, 2.5 V or 3.3 V.

CFGBVS: a board setting, not a cable setting

On 7 series, UltraScale and Zynq-7000 devices, the CFGBVS pin tells the device what voltage to expect on the configuration bank:

• VCCO_0 = 3.3 V or 2.5 V → tie CFGBVS to VCCO_0
• VCCO_0 = 1.8 V or 1.5 V → tie CFGBVS to GND

Setting it incorrectly causes configuration failure and, under some conditions, can damage the device (AMD design advisory AR 57045). It is a target-board design decision — no cable setting can change it.

Two related points:

• UltraScale+ devices (non-Zynq) have no CFGBVS pin, because their configuration I/O supports only 1.8 V and 1.5 V.
• In Vivado, the CFGBVS and CONFIG_VOLTAGE properties do not change any voltage. They exist for design rule checks. The board still decides.

The connector: 14-pin 2 mm

Xilinx’s standard JTAG header is a 2×7, 2 mm pitch connector. The signal assignment below follows Table 6 of Xilinx DS593 (Platform Cable USB II).

Things worth knowing before you connect anything:

• VREF must be a regulated supply. Do not place a current-limiting resistor between the VREF supply and pin 2.
• On older Xilinx cables (DLC9, DLC9G, DLC9LP, Parallel Cable IV), pin 13 is tied to ground. Those cables must be physically unplugged from the 2 mm header before another configuration source can access the JTAG chain.
• Pin 14 is HALT in JTAG mode. In slave-serial mode the same pin is INIT, and in SPI mode it is WP — do not mix the three up when reading a cable pinout.

Notes and caveats

Why the range stops at 5 V

The 5.0 V end of the BJ-JTAG-1’s specification is the cable’s VREF input limit — the same range Xilinx specifies for its own Platform Cable USB II (1.5 V ≤ VREF ≤ 5.0 VDC). It is not a statement about Xilinx devices, whose JTAG rails top out at 3.3 V in most families (2.5 V for Virtex-6, 3.6 V for CoolRunner-II).

Spartan-3 and Spartan-3E back-feed

Spartan-3 and Spartan-3E power their JTAG pins from VCCAUX, which is fixed at 2.5 V. If a cable drives TCK, TMS or TDI at 3.3 V into a device running at 2.5 V, the input exceeds the VIN condition, the internal clamp diode conducts, and reverse current flows into the VCCAUX rail.

Xilinx’s guidance (XAPP453, and UG332) is a series current-limiting resistor of 68 Ω or larger on TDI, TMS and TCK — 68 Ω holds the current to about 9.5 mA. Two notes on that figure:

• Earlier revisions of XAPP453 cited 56 Ω. That value is still widely repeated, but 68 Ω is the later and current figure.
• The extended Spartan-3A family does not need these resistors, because it can run VCCAUX at 3.3 V directly.

A cable that follows VREF does not have this problem, because it drives at the board’s own level rather than at a fixed 3.3 V. This note applies to fixed-voltage cables.

Virtex-6 does not support 3.3 V I/O

DS152 gives Virtex-6 a VCCO maximum of 2.625 V, so a 3.3 V configuration level sits outside the device’s recommended operating conditions. Running a device outside its recommended operating conditions risks damage and unreliable configuration. Check the level your board actually uses before connecting a fixed-voltage cable.

Which toolchain do you need?

ISE 14.7 was the last ISE release. The split is clean:

One detail that catches people out: there are two different ISE 14.7 Windows 10 packages.

• The older ISE Spartan-6 VM for Windows 10 supports Spartan-6 only — it cannot program Virtex-6.
• The later ISE 14.7 VM for Windows 10 and Windows 11 supports all ISE devices.

If you need Virtex-6 support, make sure you have the right one.

Sources

• UG470 — 7 Series FPGAs Configuration User Guide
• DS162 — Spartan-6 FPGA Data Sheet
• DS312 / UG332 / XAPP453 — Spartan-3E Data Sheet / Spartan-3 Generation Configuration User Guide / The 3.3V Configuration of Spartan-3 FPGAs
• UG191 / DS202 — Virtex-5 FPGA Configuration User Guide / Virtex-5 Data Sheet
• UG360 / DS152 — Virtex-6 FPGA Configuration User Guide / Virtex-6 Data Sheet
• DS302 / UG071 — Virtex-4 Data Sheet / Virtex-4 FPGA Configuration User Guide
• UG933 / UG585 — Zynq-7000 PCB Design Guide / Zynq-7000 Technical Reference Manual
• UG1085 / DS925 — Zynq UltraScale+ Technical Reference Manual / Data Sheet
• UG570 — UltraScale Architecture Configuration User Guide
• XAPP1220 — UltraScale Architecture BPI Configuration
• DS090 — CoolRunner-II Family Data Sheet
• DS054 / DS108-1 — XC9500XL Family Data Sheet
• DS593 — Platform Cable USB II (connector pinout)
• UG1227 — ISE 14.7 VM for Windows 10/11 installation guide
• AMD design advisory AR 57045 (CFGBVS)

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